Logic devices such as field programmable gate arrays (FPGA's) and high density programmable logic devices (HDPLD's) normally consist of a plurality of "logic blocks", each having a number of inputs and a number of outputs. Internally, the typical structure of the logic block consists of a programmable AND array whose outputs feed an OR array. FIG. 1 shows a simplified prior art logic block in the form of a programmable logic device (PLD) wherein inputs I.sub.0 and I.sub.1 feed through a programmable array 10 to four AND gates 11. The outputs of AND gates 11 feed through an array 12 to OR gates 13, and thence to outputs O.sub.0 and O.sub.1. The logic block shown in FIG. 1 is in the familiar sum of the products form, the outputs of AND gates 11 often referred to as the "product terms". In the representative structure shown in FIG. 1 either one of inputs I.sub.0 and I.sub.1 may be connected by means of the array 10 to the inputs of any one or more of AND gates 11.
In a logic device consisting of a number of individual logic blocks, any output of a logic block may need to be connected to an input of the same logic block or an input of one of the other logic blocks. This is accomplished in an area of the chip known as the interconnect area. Also, the external device inputs can routed to the logic block inputs using the interconnect area, and similarly the logic block outputs can be routed to external pins and input/output cells as outputs using the same interconnect area. The interconnect area normally comprises a matrix or latticework of intersecting input and output lines, with each output of a logic block intersecting all inputs of the same logic block and all other logic blocks once. Thus, in a device with X inputs and Y outputs, the number of such intersections equals XY.
The prior art solution to the interconnect problem is to place a programmable connection at each of the intersections, thereby allowing every output to be connected to any input of the entire device. Since each of the programmable connections takes up space, this type of arrangement increases the total size of the interconnect area and of the device itself. This increases the cost of the device. Moreover, the number of programmable connections on a given input or output line increases the loading on the line and reduces the speed of the device.